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| 1 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 mx25l3255d secure serial flash specification
2 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 contents features .................................................................................................................................................................. 5 general description ......................................................................................................................................... 7 table 1. additional feature comparison ............................................................................................................ 7 pin configurations ............................................................................................................................................. 8 pin description ...................................................................................................................................................... 8 block diagram ....................................................................................................................................................... 9 data protection .................................................................................................................................................. 1 0 table 2. 4k-bit secured otp defnition ............................................................................................................ 1 1 memory organization ............................................................................................................................................... 1 2 table 3. memory organization ........................................................................................................................ 1 2 device operation ................................................................................................................................................ 1 4 figure 1. serial modes supported .................................................................................................................... 1 4 command description ....................................................................................................................................... 1 5 table 4. command set ..................................................................................................................................... 1 5 (1) write enable (wren) ................................................................................................................................. 1 7 (2) write disable (wrdi) .................................................................................................................................. 1 7 (3) read identifcation (rdid) .......................................................................................................................... 1 7 (4) read status register (rdsr) .................................................................................................................... 1 7 (5) block write lock protection (blockp) ...................................................................................................... 1 8 (6) read block write lock status (rdblock) ................................................................................................ 1 8 (7) chip unprotect (unlock) .......................................................................................................................... 1 9 (8) read data bytes (read) ........................................................................................................................... 1 9 (9) read data bytes at higher speed (fast_read) ..................................................................................... 1 9 (10) 2 x i/o read mode (2read) .................................................................................................................... 1 9 (11) dual read mode (dread) ....................................................................................................................... 2 0 (12) 4 x i/o read mode (4read) .................................................................................................................... 2 0 (13) quad read mode (qread) ..................................................................................................................... 2 0 (14) sector erase (se) ..................................................................................................................................... 2 1 (15) block erase (be) ....................................................................................................................................... 2 1 (16) chip erase (ce) ........................................................................................................................................ 2 1 (17) page program (pp) ................................................................................................................................... 2 2 (18) 4 x i/o page program (4pp) ..................................................................................................................... 2 2 (19) continuously program mode (cp mode) .................................................................................................. 2 2 (20) deep power-down (dp) ............................................................................................................................ 2 3 (21) release from deep power-down (rdp), read electronic signature (res) ............................................ 2 3 (22) read electronic manufacturer id & device id (rems), (rems2), (rems4) .......................................... 2 4 table 5. id defnitions ..................................................................................................................................... 2 4 (23) enter secured otp (enso) ..................................................................................................................... 2 5 (24) exit secured otp (exso) ........................................................................................................................ 2 5 3 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 (25) read security register (rdscur) .......................................................................................................... 2 5 table 6. security register defnition ................................................................................................................ 2 6 (26) write security register (wrscur) .......................................................................................................... 2 6 power-on state ................................................................................................................................................... 2 7 electrical specifications .............................................................................................................................. 2 8 absolute maximum ratings ................................................................................................................... 2 8 figure 2.maximum negative overshoot waveform ......................................................................................... 2 8 capacitance ta = 25c, f = 1.0 mhz ........................................................................................................... 2 8 figure 3. maximum positive overshoot waveform .......................................................................................... 2 8 figure 4. input test waveforms and measurement level ............................................................ 2 9 figure 5. output loading ......................................................................................................................... 2 9 table 7. dc characteristics (temperature = -40 c to 85 c for industrial grade, vcc = 2.7v ~ 3.6v) . 3 0 table 8. ac characteristics (temperature = -40c to 85c for industrial grade, vcc = 2.7v ~ 3.6v) 3 1 timing analysis ........................................................................................................................................................ 3 2 figure 6. serial input timing ............................................................................................................................ 3 2 figure 7. output timing .................................................................................................................................... 3 2 figure 8. wp# setup timing and hold timing ................................................................................................ 3 3 figure 9. write enable (wren) sequence (command 06) ............................................................................. 3 3 figure 10. write disable (wrdi) sequence (command 04) ............................................................................ 3 3 figure 11. read identifcation (rdid) sequence (command 9f) .................................................................... 3 4 figure 12. read status register (rdsr) sequence (command 05) .............................................................. 3 4 figure 13. block write lock protection (blockp) sequence (command e2) ............................................... 3 4 figure 14. chip unprotect (unlock) sequence (command f3) .................................................................. 3 5 figure 15. read data bytes (read) sequence (command 03) .................................................................... 3 5 figure 16. read block protection lock status (rdblock) sequence (command fb) ................................ 3 5 figure 17. read at higher speed (fast_read) sequence (command 0b) ................................................ 3 6 figure 18. 2 x i/o read mode sequence (command bb) ............................................................................... 3 6 figure 19. dual read mode sequence (command 3b) ................................................................................... 3 7 figure 20. 4 x i/o read mode sequence (command eb) ............................................................................... 3 7 figure 21. 4 x i/o read enhance performance mode sequence (command eb) ........................................... 3 8 figure 22. quad read mode sequence (command 6b) ................................................................................. 3 9 figure 23. page program (pp) sequence (command 02) .............................................................................. 4 0 figure 24. 4 x i/o page program (4pp) sequence (command 38) ................................................................ 4 0 figure 25. continously program (cp) mode sequence with hardware detection (command ad) ................. 4 1 figure 26. sector erase (se) sequence (command 20) ................................................................................ 4 1 figure 27. block erase (be) sequence (command d8) ................................................................................. 4 1 figure 28. chip erase (ce) sequence (command 60 or c7) ......................................................................... 4 2 figure 29. deep power-down (dp) sequence (command b9) ....................................................................... 4 2 figure 30. release from deep power-down and read electronic signature (res) sequence (command ab) ......................................................................................................................................................................... 4 2 figure 31. release from deep power-down (rdp) sequence (command ab) ............................................. 4 3 figure 32. read electronic manufacturer & device id (rems) sequence (command 90 or ef or df) ........ 4 3 4 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 33. power-up timing ............................................................................................................................. 4 4 table 9. power-up timing ............................................................................................................................... 4 4 initial delivery state ............................................................................................................................... 4 4 operating conditions ....................................................................................................................................... 4 5 figure 34. ac timing at device power-up ....................................................................................................... 4 5 figure 35. power-down sequence .................................................................................................................. 4 6 erase and programming performance .................................................................................................... 4 7 data retention .................................................................................................................................................... 4 7 latch-up characteristics .............................................................................................................................. 4 7 ordering information ...................................................................................................................................... 4 8 part name description ..................................................................................................................................... 4 9 package information ........................................................................................................................................ 5 0 revision history ................................................................................................................................................. 5 2 5 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 features general ? serial peripheral interface compatible -- mode 0 and mode 3 ? 33,554,432 x 1 bit structure or 16,772,216 x 2 bits (two i/o read mode) structure or 8,388,608 x 4 bits (four i/o read mode) structure ? 1024 equal sectors with 4k byte each - any sector can be erased individually ? 64 equal blocks with 64k byte each - any block can be erased individually ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to vcc +1v performance ? high performance - fast read - 1 i/o: 104mhz with 8 dummy cycles - 4 i/o: 75mhz with 6 dummy cycles for 4read; 75mhz with 8 dummy cycles for qread - 2 i/o: 75mhz with 4 dummy cycles for 2read; 75mhz with 8 dummy cycles for dread - fast access time: 104mhz serial clock - serial clock of four i/o read mode : 75mhz, which is equivalent to 300mhz - fast program time: 1.4ms(typ.) and 5ms(max.)/page (256-byte per page) - byte program time: 9us (typical) - continuously program mode (automatically increase address under word program mode) - fast erase time: 60ms (typ.)/sector (4k-byte per sector) ; 0.7s(typ.) /block (64k-byte per block); 25s(typ.) /chip ? low power consumption - low active read current: 25ma(max.) at 104mhz, 20ma(max.) at 66mhz and 10ma(max.) at 33mhz - low active programming current: 20ma (max.) - low active erase current: 20ma (max.) - low standby current: 20ua (max.) ? typical 100,000 erase/program cycles ? 20 years data retention software features ? input data format - 1-byte command code ? advanced security features - block write lock protection - additional 4k-bit secured otp for unique identifer - permanent lock - read protection function ? auto erase and auto program algorithm - automatically erases and verifes data at selected sector - automatically programs and verifes data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state frst) 32m-bit [x 1/x 2/x4] cmos mxsmio tm (serial multi i/o) flash memory 6 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 ? status register feature ? electronic identifcation - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - both rems,rems2 and rems4 commands for 1-byte manufacturer id and 1-byte device id hardware features ? sclk input - serial clock input ? si/sio0 - serial data input or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? so/sio1 - serial data output or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? wp#/sio2 - hardware write protection or serial data input/output for 4 x i/o read mode ? nc/sio3 - nc pin or serial data input/output for 4 x i/o read mode ? package - 8-pin sop (200mil) - 24-ball bga - all pb-free devices are rohs compliant please contact macronix sales for specifc information regarding this advanced security features 7 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 table 1. additional feature comparison general description the mx25l3255d are 33,554,432 bit serial flash memory, which is confgured as 4,194,304 x 8 internally. when it is in two or four i/o read mode, the structure becomes 16,772,216 bits x 2 or 8,388,608 bits x 4. the mx25l3255d feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. when it is in two i/o read mode, the si pin and so pin become sio0 pin and sio1 pin for address/dummy bits in - put and data output. when it is in four i/o read mode, the si pin, so pin, wp# pin and nc pin become sio0 pin, sio1 pin, sio2 pin and sio3 pin for address/dummy bits input and data output. the mx25l3255d provides sequential read operation on whole chip. after program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specifed page or sector/block locations will be executed. program command is executed on byte basis, or page (256 bytes) basis, or word basis for continuously program mode, and erase command is executes on sector (4k-byte), or block (64k-byte), or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. advanced security features enhance the protection and security functions, please contact macronix sales for more details. when the device is not in operation and cs# is high, it is put in standby mode and draws less than 20ua dc cur - rent. the mx25l3255d utilizes macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. additional features part name protection and security read performance identifer perman- ent lock each block protection 4k-bit secured otp wp# hardware protection read protect- ion 2 i/o read (75 mhz) 4 i/o read (75 mhz) res (command: 90 hex) rems/2/4 (command: 90/ef/0f hex) rdid (command: 9f hex) mx25l3255d v v v v v v v 9e (hex) c2 9e (hex) c2 9e 16 (hex) mx25l3235d v v v v 5e (hex) c2 5e (hex) c2 5e 16 (hex) 8 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 pin configurations pin description 8-pin sop (200mil) symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) so/sio1 serial data output (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) sclk clock input wp#/sio2 write protection: connect to gnd or serial data input & output (for 4xi/o read mode) nc/sio3 nc pin (not connect) or serial data input & output (for 4xi/o read mode) vcc + 3.3v power supply gnd ground 1 2 3 4 cs# so/sio1 wp#/sio2 gnd vcc nc/sio3 sclk si/sio0 8 7 6 5 24-ball bga 4 3 2 1 a b c d e f vcc wp#/sio2 nc/sio3 nc gnd si/sio0 nc sclk cs# so/sio1 nc nc nc nc nc nc nc nc nc nc nc nc nc nc 9 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk so/sio1 clock generator state machine mode logic sense amplifier hv generator output buffer cs# wp#/sio2 nc/sio3 10 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 data protection mx25l3255d is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically resets the state ma - chine in the standby mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specifc command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transition or system noise. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - write disable (wrdi) command completion - page program (pp) command completion - continuously program mode (cp) instruction completion - sector erase (se) command completion - block erase (be) command completion - chip erase (ce) command completion ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic sig - nature command (res). ? advanced security features: there are some protection and securuity features which protect content from inad - vertent write and hostile access. i. block write lock protection - the software protected mode (spm) use a23-a16 address bits to allow a block (64k byte) of memory to be protected as read only through the block write lock protection command (blockp). this feature allows user to unprotect the entice chip through the chip unprotect command (unlock). - the hardware protected mode (hpm) use wp#/sio2 to protect the block. if wp#/sio2=vil (input low), all blocks of memory to be protected as read only. if wp#/sio2=vih (input high), all blocks depends on whether they were last lock or unlock. if the system goes into four i/o read mode, the feature of hpm will be disabled. 11 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 ii. additional 4k-bit secured otp for unique identifer: to provide 4k-bit one-time program area for setting device unique serial number - which may be set by factory or system customer. please refer to table 2. 4k-bit secured otp defnition. - security register bit 0 indicates whether the chip is locked by factory or not. - to program the 4k-bit secured otp by entering 4k-bit secured otp mode (with enso command), and going through normal program procedure, and then exiting 4k-bit secured otp mode by writing exso command. - customer may lock-down the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to table of "security register defnition" for security register bit defnition and table of "4k-bit secured otp defnition" for address range defnition. - note: once lock-down whatever by factory or customer, it cannot be changed any more. while in 4k-bit se - cured otp mode, array access is not allowed. table 2. 4k-bit secured otp defnition address range size standard factory lock customer lock xxx000~xxx00f 128-bit esn (electrical serial number) determined by customer xxx010~xxx1ff 3968-bit n/a 12 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 table 3. memory organization memory organization block sector address range 63 1023 3ff000h 3fffffh : : : 1008 3f0000h 3f0fffh 62 1007 3ef000h 3effffh : : : 992 3e0000h 3e0fffh 61 991 3df000h 3dffffh : : : 976 3d0000h 3d0fffh 60 975 3cf000h 3cffffh : : : 960 3c0000h 3c0fffh 59 959 3bf000h 3bffffh : : : 944 3b0000h 3b0fffh 58 943 3af000h 3affffh : : : 928 3a0000h 3a0fffh 57 927 39f000h 39ffffh : : : 912 390000h 390fffh 56 911 38f000h 38ffffh : : : 896 380000h 380fffh 55 895 37f000h 37ffffh : : : 880 370000h 370fffh 54 879 36f000h 36ffffh : : : 864 360000h 360fffh 53 863 35f000h 35ffffh : : : 848 350000h 350fffh 52 847 34f000h 34ffffh : : : 832 340000h 340fffh 51 831 33f000h 33ffffh : : : 816 330000h 330fffh 50 815 32f000h 32ffffh : : : 800 320000h 320fffh 49 799 31f000h 31ffffh : : : 784 310000h 310fffh 48 783 30f000h 30ffffh : : : 768 300000h 300fffh block sector address range 47 767 2ff000h 2fffffh : : : 752 2f0000h 2f0fffh 46 751 2ef000h 2effffh : : : 736 2e0000h 2e0fffh 45 735 2df000h 2dffffh : : : 720 2d0000h 2d0fffh 44 719 2cf000h 2cffffh : : : 704 2c0000h 2c0fffh 43 703 2bf000h 2bffffh : : : 688 2b0000h 2b0fffh 42 687 2af000h 2affffh : : : 672 2a0000h 2a0fffh 41 671 29f000h 29ffffh : : : 656 290000h 290fffh 40 655 28f000h 28ffffh : : : 640 280000h 280fffh 39 639 27f000h 27ffffh : : : 624 270000h 270fffh 38 623 26f000h 26ffffh : : : 608 260000h 260fffh 37 607 25f000h 25ffffh : : : 592 250000h 250fffh 36 591 24f000h 24ffffh : : : 576 240000h 240fffh 35 575 23f000h 23ffffh : : : 560 230000h 230fffh 34 559 22f000h 22ffffh : : : 544 220000h 220fffh 33 543 21f000h 21ffffh : : : 528 210000h 210fffh 32 527 20f000h 20ffffh : : : 512 200000h 200fffh 13 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 block sector address range 31 511 1ff000h 1fffffh : : : 496 1f0000h 1f0fffh 30 495 1ef000h 1effffh : : : 480 1e0000h 1e0fffh 29 479 1df000h 1dffffh : : : 464 1d0000h 1d0fffh 28 463 1cf000h 1cffffh : : : 448 1c0000h 1c0fffh 27 447 1bf000h 1bffffh : : : 432 1b0000h 1b0fffh 26 431 1af000h 1affffh : : : 416 1a0000h 1a0fffh 25 415 19f000h 19ffffh : : : 400 190000h 190fffh 24 399 18f000h 18ffffh : : : 384 180000h 180fffh 23 383 17f000h 17ffffh : : : 368 170000h 170fffh 22 367 16f000h 16ffffh : : : 352 160000h 160fffh 21 351 15f000h 15ffffh : : : 336 150000h 150fffh 20 335 14f000h 14ffffh : : : 320 140000h 140fffh 19 319 13f000h 13ffffh : : : 304 130000h 130fffh 18 303 12f000h 12ffffh : : : 288 120000h 120fffh 17 287 11f000h 11ffffh : : : 272 110000h 110fffh 16 271 10f000h 10ffffh : : : 256 100000h 100fffh 15 255 0ff000h 0fffffh : : : 240 0f0000h 0f0fffh block sector address range 14 239 0ef000h 0effffh : : : 224 0e0000h 0e0fffh 13 223 0df000h 0dffffh : : : 208 0d0000h 0d0fffh 12 207 0cf000h 0cffffh : : : 192 0c0000h 0c0fffh 11 191 0bf000h 0bffffh : : : 176 0b0000h 0b0fffh 10 175 0af000h 0affffh : : : 160 0a0000h 0a0fffh 9 159 09f000h 09ffffh : : : 144 090000h 090fffh 8 143 08f000h 08ffffh : : : 128 080000h 080fffh 7 127 07f000h 07ffffh : : : 112 070000h 070fffh 6 111 06f000h 06ffffh : : : 96 060000h 060fffh 5 95 05f000h 05ffffh : : : 80 050000h 050fffh 4 79 04f000h 04ffffh : : : 64 040000h 040fffh 3 63 03f000h 03ffffh : : : 48 030000h 030fffh 2 47 02f000h 02ffffh : : : 32 020000h 020fffh 1 31 01f000h 01ffffh : : : 16 010000h 010fffh 0 15 00f000h 00ffffh : : : 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh 14 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended op - eration. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, so pin of this lsi should be high-z. 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as figure 1. 5. for the following instructions: rdid, rdsr, rdscur, read, fast_read, 2read, dread, 4read, qread, rdblock, rdplock, res, rems, rems2 and rems4 the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrlb, se, be, ce, pp, 4pp, cp, rdp, dp, blockp, unlock, enso, and exso, the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of write status register, program, erase operation, to access the memory array is neglect - ed and not affect the current operation of write status register, program, erase. figure 1. serial modes supported note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb 15 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 command description table 4. command set command (byte) wren (write enable) wrdi (write disable) rdid (read identifcation) rdsr (read status register) blockp (block write lock protection) rdblock (read block write lock status) unlock (chip unprotect) read (read data) 1st byte 06 (hex) 04 (hex) 9f (hex) 05 (hex) e2 (hex) fb (hex) f3 (hex) 03 (hex) 2nd byte ad1 ad1 ad1 (a23-a16) 3rd byte ad2 ad2 ad2 (a15-a8) 4th byte ad3 ad3 ad3 (a7-a0) action sets the (wel) write enable latch bit resets the (wel) write enable latch bit outputs jedec id: 1-byte manufacturer id & 2-byte device id to read out the values of the status register assign a block (64kb) to lock protection read assigned block write lock status reset block write lock protection bit whole chip n bytes read out until cs# goes high command (byte) fast read (fast read data) 2read (2 x i/o read command) note1 dread (1i 2o read command) 4read (4 x i/o read command) qread (1i 4o read command) release read enhanced 4pp (quad page program) se (sector erase) 1st byte 0b (hex) bb (hex) 3b (hex) eb (hex) 6b (hex) ff (hex) 38 (hex) 20 (hex) 2nd byte ad1 add(2) ad1 add(4) & dummy(4) ad1 x ad1 ad1 3rd byte ad2 add(2) & dummy(2) ad2 dummy(4) ad2 x ad2 4th byte ad3 ad3 ad3 x ad3 5th byte dummy dummy dummy action n bytes read out until cs# goes high n bytes read out by 2 x i/ o until cs# goes high n bytes read out by dual output until cs# goes high n bytes read out by 4 x i/ o until cs# goes high n bytes read out by quad output until cs# goes high all these commands ffh,00h,aah or 55h will escape the performance enhance mode quad input to program the selected page to erase the selected sector command (byte) be (block erase) ce (chip erase) pp (page program) cp (continuously program mode) dp (deep power down) rdp (release from deep power down) res (read electronic id) rems (read electronic manufacturer & device id) 1st byte d8 (hex) 60 or c7 (hex) 02 (hex) ad (hex) b9 (hex) ab (hex) ab (hex) 90 (hex) 2nd byte ad1 ad1 ad1 x x 3rd byte ad2 ad2 ad2 x x 4th byte ad3 ad3 ad3 x add (note 2) action to erase the selected block to erase whole chip to program the selected page continously program whole chip, the address is automatically increase enters deep power down mode release from deep power down mode to read out 1-byte device id output the manufacturer id & device id 16 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 note 1: the count base is 4-bit for add(2) and dummy(2) because of 2 x i/o. and the msb is on si/sio1 which is different from 1 x i/o condition. note 2: add=00h will output the manufacturer id frst and add=01h will output device id frst. note 3: it is not allowed to adopt any other code which is not in the above command defnition table. command (byte) rems2 (read id for 2x i/o mode) rems4 (read id for 4x i/o mode) enso (enter secured otp) exso (exit secured otp) rdscur (read security register) wrscur (write security register) esry (enable so to output ry/ by#) dsry (disable so to output ry/ by#) 1st byte ef (hex) df (hex) b1 (hex) c1 (hex) 2b (hex) 2f (hex) 70 (hex) 80 (hex) 2nd byte x x 3rd byte x x 4th byte add (note 2) add (note 2) action output the manufacturer id & device id output the manufact- urer id & device id to enter the 4k-bit secured otp mode to exit the 4k-bit secured otp mode to read value of security register to set the lock-down bit as "1" (once lock-down, cannot be updated) to enable so to output ry/ by# during cp mode to disable so to output ry/ by# during cp mode 17 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 (1) write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, 4pp, blockp, plock, unlock, cp, se, be, and ce which are intended to change the device content, should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes low sending wren instruction code cs# goes high. (see figure 9) (2) write disable (wrdi) the write disable (wrdi) instruction is for resetting write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes low sending wrdi instruction code cs# goes high. (see figure 10) the wel bit is reset by following situations: - power-up - write disable (wrdi) instruction completion - page program (pp) instruction completion - quad page program (4pp) instruction completion - sector erase (se) instruction completion - block erase (be) instruction completion - chip erase (ce) instruction completion - continuously program mode (cp) instruction completion - block write lock protection (blockp) instruction completion - chip unprotect (unlock) instruction completion (3) read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the mxic manufacturer id is c2(hex), the memory type id is 9e (hex) as the frst-byte device id, and the individual device id of second-byte id are listed as table of "id defnitions". (see table 5) the sequence of issuing rdid instruction is: cs# goes low sending rdid instruction code 24-bits id data out on so to end rdid operation can use cs# to high at any time during data out. (see figure 1 1.) while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cy - cle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. (4) read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes low sending rdsr instruction code status register data out on so (see figure 12) the defnition of the status register bits is as below: 18 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 status register (5) block write lock protection (blockp) the blockp instruction is for write protection a specifed block of memory, using a23-a16 (a15-a0 don't care) ad - dress bits to assign a 64kbyte block to be protected as read only. this feature allows user to stop protecting the en - tire block through the chip unprotect command (unlock). the wren (write enable) instruction is required before issuing blockp instruction. the sequence of issuing blockp instruction is: cs# goes lowsend blockp (e2h) instruction send 3 address bytes assign one block to be protected on si pin cs# goes high. (see figure 13) the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. (6) read block write lock status (rdblock) the rdplock instruction is for reading the status of permanent lock of a specifed block, using a23-a16 (a15-a0 =0) address bits to assign a 64kbyte block and read permanent lock status bit which the frst byte of read-out cycle. the frst byte data out dq0 is"1" to indicate that this block has be locked permanently, that user can read only but cannot write, program or erase this block permanently. the frst byte data out dq0 is "0" to indicate that this block hasn't be protected, and user can read and write this block. the sequence of issuing rdblock instruction is: cs# goes low send rdblock (fbh) instruction send 3 ad - dress bytes to assign one block on si pin read block's protection lock status bit on so pin cs# goes high. (see figure 16) wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the de - vice will not accept program/erase/write status register instruction. the program/erase command will be ignored and not affect value of wel bit if it is applied to a protected memory area. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 x x x x x x wel (write enable latch) wip (write in progress bit) reserved reserved reserved reserved reserved reserved 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit 19 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 (7) chip unprotect (unlock) the unlock instruction is for disabling the lock protection block of the whole chip. the wren (write enable) instruction is required before issuing unlock instruction. the sequence of issuing unlock instruction is: cs# goes low send unlock (f3h) instruction cs# goes high. (see figure 14) the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. (8) read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes low sending read instruction code 3-byte address on si data out on soto end read operation can use cs# to high at any time during data out. (see figure 15) (9) read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code-> 3-byte address on si 1-dummy byte (default) address on sidata out on so to end fast_read operation can use cs# to high at any time during data out. (see figure 17) while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any im - pact on the program/erase/write status register current cycle. (10) 2 x i/o read mode (2read) the 2read instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits(interleave on 2 i/o pins) shift out on the falling edge of sclk at a maxi - mum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2read instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing 2read instruc - tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing 2read instruction is: cs# goes low o sending 2read instruction o 24-bit address inter - leave on sio1 & sio0 o 4-bit dummy cycle on sio1 & sio0 o data out interleave on sio1 & sio0 o to end 2read operation can use cs# to high at any time during data out (see figure 18 for 2 x i/o read mode timing waveform). while program/erase/write status register cycle is in progress, 2read instruction is rejected without any impact on the program/erase/write status register current cycle. 20 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 (11) dual read mode (dread) the dread instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits(interleave on 2 i/o pins) shift out on the falling edge of sclk at a maxi - mum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dread instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing dread instruc - tion, the following data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing dread instruction is: cs# goes low sending dread instruction 3-byte address on sio0 8-bit dummy cycle on sio0 data out interleave on sio1 & sio0 to end 2read operation can use cs# to high at any time during data out (see figure 19 for dual read mode timing waveform). while program/erase/write status register cycle is in progress, dread instruction is rejected without any impact on the program/erase/write status register current cycle. (12) 4 x i/o read mode (4read) the 4read instruction enable quad throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every four bits(interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 4read instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing 4read instruc - tion, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing 4read instruction is: cs# goes low sending 4read instruction 24-bit address inter - leave on sio3, sio2, sio1 & sio0 6 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out (see figure 20 for 4 x i/o read mode tim - ing waveform). another sequence of issuing 4 read instruction especially useful in random access is : cs# goes low sending 4 read instruction 3-bytes address interleave on sio3, sio2, sio1 & sio0 performance enhance toggling bit p[7:0] 4 dummy cycles data out still cs# goes high cs# goes low (reduce 4 read instruction) 24-bit ran - dom access address (see figure 21 for 4x i/o read enhance performance mode timing waveform). in the performance-enhancing mode, p[7:4] must be toggling with p[3:0] ; likewise p[7:0]=a5h,5ah,f0h or 0fh can make this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh,00h,aah or 55h. and afterwards cs# is raised or issuing ff command(cs# goes high -> cs# goes low -> sending 0xff -> cs# goes high) instead of no toggling,the system then will escape from performance enhance mode and return to normal opertaion.in these cases,tshsl=15ns(min) will be specifed. while program/erase cycle is in progress, 4read instruction is rejected without any impact on the program/erase current cycle. (13) quad read mode (qread) the qread instruction enable quad throughput of serial flash in read mode. a quad enable (qe) bit of status register must be set to "1" before seding the qread instruction.the address is latched on rising edge of sclk, and data of every four bits(interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address 21 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 after each byte data is shifted out, so the whole memory can be read out at a single qread instruction. the ad - dress counter rolls over to 0 when the highest address has been reached. once writing qread instruction, the fol - lowing data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing qread instruction is: cs# goes low sending qread instruction 24-bit address on sio0 8 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end qread operation can use cs# to high at any time during data out (see figure 22 for quad read mode timing waveform). while program/erase/write status register cycle is in progress, qread instruction is rejected without any impact on the program/erase/write status register current cycle. (14) sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see table 3) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most signifcant address) select the sector address. the sequence of issuing se instruction is: cs# goes low sending se instruction code 3-byte address on si cs# goes high. (see figure 26) the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the sector is protected, the sector erase (se) instruction will not be executed on the sector. (15) block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (see table 3) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code 3-byte address on si cs# goes high. (see figure 27) the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected, the block erase (be) instruction will not be executed on the block. &kls(udvh&( the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruc - tion must execute to set the write enable latch (wel) bit before sending the chip erase (ce). the cs# must go 22 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes low sending ce instruction code cs# goes high. (see figure 28) the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. (17) page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). the device pro - grams only the last 256 data bytes sent to the device. if the entire 256 data bytes are going to be programmed, a7- a0 (the eight least signifcant address bits) should be set to 0. if the eight least signifcant address bits (a7-a0) are not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of the same page (from the address a7-a0 are all 0). if more than 256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and previous data will be disregarded. if less than 256 bytes are sent to the device, the data is programmed at the requested address of the page without effect on other address of the same page. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code3-byte address on si at least 1-byte on data on si cs# goes high. (see figure 23) the cs# must be kept to low during the whole page program cycle; the cs# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be ex - ecuted. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected, the page program (pp) instruction will not be executed. (18) 4 x i/o page program (4pp) the quad page program (4pp) instruction is for programming the memory to be "0". a write enable (wren) in - struction must execute to set the write enable latch (wel) bit. the quad page programming takes four pins: sio0, sio1, sio2, and sio3 as address and data input, which can improve programer performance and the ef - fectiveness of application of lower clock less than 20mhz. for system with faster clock, the quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data fows in. therefore, we suggest that while executing this command (especially during sending data), user can slow the clock speed down to 20mhz below. the other function descriptions are as same as standard page program. the sequence of issuing 4pp instruction is: cs# goes low sending 4pp instruction code 3-byte address on sio[3:0] at least 1-byte on data on sio[3:0] cs# goes high. (see figure 24) (19) continuously program mode (cp mode) the cp mode may enhance program performance by automatically increasing address to the next higher address after each byte data has been programmed. 23 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 the continuously program (cp) instruction is for multiple byte program to flash. a write enable (wren) instruc - tion must execute to set the write enable latch(wel) bit before sending the continuously program (cp) instruction. cs# requires to go high before cp instruction is executing. after cp instruction and address input, two bytes of data is input sequentially from msb(bit7) to lsb(bit0). the frst byte data will be programmed to the initial address range with a0=0 and second byte data with a0=1. if only one byte data is input, the cp mode will not process. if more than two bytes data are input, the additional data will be ignored and only two byte data are valid. the cp program instruction will be ignored and not affect the wel bit if it is applied to a protected memory area. any byte to be pro - grammed should be in the erase state (ff) frst. it will not roll over during the cp mode, once the last unprotected address has been reached, the chip will exit cp mode and reset write enable latch bit (wel) as "0" and cp mode bit as "0". please check the wip bit status if it is not in write progress before entering next valid instruction. during cp mode, the valid commands are cp command (ad hex), wrdi command (04 hex), rdsr command (05 hex), and rdscur command (2b hex). and the wrdi command is valid after completion of a cp programming cycle, which means the wip bit=0. the sequence of issuing cp instruction is : cs# high to low sending cp instruction code 3-byte address on si-> data byte on sics# goes high to lowsending cp instruction...... last desired byte programmed or sending write disable (wrdi) instruction to end cp mode sending rdsr instruction to verify if cp mode is ended. (see figure 25 of cp mode timing waveform) three methods to detect the completion of a program cycle during cp mode: 1) software method-i: by checking wip bit of status register to detect the completion of cp mode. 2) software method-ii: by waiting for a tbp time out to determine if it may load next valid command or not. 3) hardware method: by writing esry (enable so to output ry/by#) instruction to detect the completion of a program cycle during cp mode. the esry instruction must be executed before cp mode execution. once it is enable in cp mode, the cs# goes low will drive out the ry/by# status on so, "0" indicates busy stage, "1" indi - cates ready stage, so pin outputs tri-state if cs# goes high. dsry (disable so to output ry/by#) instruction to disable the so to output ry/by# and return to status register data output during cp mode. please note that the esry/dsry command are not accepted unless the completion of cp mode. (20) deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (to enter - ing the deep power-down mode), the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not ac - tive and all write/program/erase instruction are ignored. when cs# goes high, it's only in standby mode not deep power-down mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes lowsending dp instruction code cs# goes high. (see fig - ure 29) once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction. (those instructions allow the id being reading out). when power- down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode and reducing the current to isb2. (21) release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the 24 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specifed in table 8. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id defnitions. this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. the sequence is shown as figure 30, 31. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeat - edly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. the rdp instruction is for releasing from deep power down mode. (22) read electronic manufacturer id & device id (rems), (rems2), (rems4) the rems, rems2 & rems4 instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specifc device id. the rems, rems2 & rems4 instruction is very similar to the release from power-down/device id instruction. the instruction is initiated by driving the cs# pin low and shift the instruction code "90h" or "efh" or "dfh"followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id for mxic (c2h) and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst as shown in figure 32. the device id values are listed in table of id defnitions. if the one-byte address is initially set to 01h, then the device id will be read frst and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. table 5. id defnitions rdid command manufacturer id memory type memory density c2 9e 16 res command electronic id 9e rems/rems2/rems4/ command manufacturer id device id c2 9e 25 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 (23) enter secured otp (enso) the enso instruction is for entering the additional 4k-bit secured otp mode. the additional 4k-bit secured otp is independent from main array, which may use to store unique serial number for system identifer. after entering the secured otp mode, and then follow standard read or program, procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes low sending enso instruction to enter secured otp mode cs# goes high. please note that wrscur commands is not acceptable during the access of secure otp region, once security otp is lock down, only read related commands are valid. (24) exit secured otp (exso) the exso instruction is for exiting the additional 4k-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes low sending exso instruction to exit secured otp mode cs# goes high. (25) read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write parameter register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : cs# goes low send ing rdscur instruction security regis - ter data out on so cs# goes high. the defnition of the security register bits is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory before ex- factory or not. when it is "0", it indicates non- factory lock; "1" indicates factory- lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for cus - tomer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 4k-bit secured otp area cannot be update any more. while it is in 4k-bit secured otp mode, array access is not allowed. continuously program mode (cp mode) bit. the continuously program mode bit indicates the status of cp mode, "0" indicates not in cp mode; "1" indicates in cp mode. 26 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 table 6. security register defnition (26) write security register (wrscur) the wrscur instruction is for changing the values of security register bits. the wren instruction is not required before sending wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 4k-bit secured otp area. once the ldso bit is set to "1", the secured otp area cannot be updated any more. the sequence of issuing wrscur instruction is :cs# goes low sending wrscur instruction cs# goes high. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 x x x continuously program mode (cp mode) x x ldso (indicate if lock-down secured otp indicator bit reserved reserved reserved 0=normal program mode 1=cp mode (default=0) reserved reserved 0 = not lock- down 1 = lock-down (cannot program/erase otp) 0 = non-factory lock 1 = factory lock volatile bit volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit non-volatile bit 27 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 power-on state the device is at below states when power-up: - standby mode ( please note it is not deep power-down mode) - write enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power-up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the read, write, erase, and program command should be sent after the time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. please refer to the fgure of "power-up timing". note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommend - ed. (generally around 0.1uf) 28 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 absolute maximum ratings electrical specifications capacitance ta = 25c, f = 1.0 mhz notice: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. ex - posure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot vss to -2.0v and vcc to +2.0v for periods up to 20ns, see figure 2, 3. figure 2.maximum negative overshoot waveform figure 3. maximum positive overshoot waveform symbol parameter min. typ max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to 4.6v applied output voltage -0.5v to 4.6v vcc to ground potential -0.5v to 4.6v vss vss-2.0v 20ns 20ns 20ns vcc + 2.0v vcc 20ns 20ns 20ns 29 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 4. input test waveforms and measurement level figure 5. output loading ac measurement level input timing referance level output timing referance level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm +3.3v cl=30pf including jig capacitance 30 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 table 7. dc characteristics (temperature = -40 c to 85 c for industrial grade, vcc = 2.7v ~ 3.6v) notes : 1. typical values at vcc = 3.3v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation. symbol parameter notes min. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vin = vcc or gnd isb1 vcc standby current 1 20 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 20 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 25 ma f=104mhz, fq=75mhz (4 x i/o read) sclk=0.1vcc/0.9vcc, so=open 20 ma f=66mhz, ft=75mhz (2 x i/o read) sclk=0.1vcc/0.9vcc, so=open 10 ma f=33mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 20 ma program in progress, cs# = vcc icc4 vcc sector erase current (se) 1 20 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 20 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.3vcc v vih input high voltage 0.7vcc vcc+0.4 v vol output low voltage 0.4 v iol = 1.6ma voh output high voltage vcc-0.2 v ioh = -100ua 31 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 table 8. ac characteristics (temperature = -40c to 85c for industrial grade, vcc = 2.7v ~ 3.6v) notes: 1. tch + tcl must be greater than or equal to 1/ f (fc or fr). 2. value guaranteed by characterization, not 100% tested in production. 3. tshsl=15ns from read instruction, tshsl=50ns from write/erase/program instruction. 4. test condition is shown as figure 4, 5. symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, pp, se, be, ce, dp, res,rdp wren, wrdi, rdid, rdsr, wrsr d.c. 104 mhz frsclk fr clock frequency for read instructions 33 mhz ftsclk ft clock frequency for 2read, dread instructions 75 mhz fq clock frequency for 4read, qraed instructions 75 mhz fpsclk fp clock frequency for 4pp operation 20 mhz tch(1) tclh clock high time fc=104mhz 4.7 ns fr=33mhz 13 ns tcl(1) tcll clock low time fc=104mhz 4.7 ns fr=33mhz 13 ns tclch(2) clock rise time (3) (peak to peak) 0.1 v/ns tchcl(2) clock fall time (3) (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 5 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 5 ns tchsh cs# active hold time (relative to sclk) 5 ns tshch cs# not active setup time (relative to sclk) 5 ns tshsl(3) tcsh cs# deselect time read 15 ns write/erase/program 50 ns tshqz(2) tdis output disable time loading: 30pf/15pf 2.7v-3.6v 10/8 ns 3.0v-3.6v 8/6 ns tclqv tv clock low to output valid loading: 30pf/15pf 2.7v-3.6v 10/8 ns 3.0v-3.6v 8/6 ns tclqx tho output hold time 0 ns twhsl(4) write protect setup time 20 ns tshwl(4) write protect hold time 100 ns tdp(2) cs# high to deep power-down mode 10 us tres1(2) cs# high to standby mode without electronic signature read 8.8 us tres2(2) cs# high to standby mode with electronic signature read 8.8 us tu chip unprotect time 40 100 ms tbp byte-program 9 300 us tpp page program cycle time 1.4 5 ms tse sector erase cycle time 60 300 ms tbe block erase cycle time 0.7 2 s tce chip erase cycle time 25 50 s 32 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 6. serial input timing figure 7. output timing timing analysis sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si 33 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 8. wp# setup timing and hold timing figure 9. write enable (wren) sequence (command 06) figure 10. write disable (wrdi) sequence (command 04) high-z 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so 2 1 34567 high-z 0 06 command sclk si cs# so 2 1 34567 high-z 0 04 command sclk si cs# so 34 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 11. read identifcation (rdid) sequence (command 9f) figure 12. read status register (rdsr) sequence (command 05) figure 13. block write lock protection (blockp) sequence (command e2) 2 1 3456789 10 11 12 13 14 15 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9f 2 1 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05 24 bit address 2 1 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si e2 command 35 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 14. chip unprotect (unlock) sequence (command f3) figure 15. read data bytes (read) sequence (command 03) figure 16. read block protection lock status (rdblock) sequence (command fb) 2 1 34567 0 f3 sclk si cs# command sclk si cs# so 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03 high-z command 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 39 40 41 42 43 44 45 46 47 765432 0 1 high-z block protection lock status out 3 address bytes 1 dummy bytes dummy 0 msb msb sclk cs# si so fb command 36 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 17. read at higher speed (fast_read) sequence (command 0b) 23 2 1 3456789 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 configurable dummy cycle msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35 sclk si cs# so sclk si cs# so 0b command figure 18. 2 x i/o read mode sequence (command bb) high impedance 2 1 345678 0 sclk si/sio0 so/sio1 cs# 9 10 11 18 19 20 bb(hex) dummy dummy address bit22, bit20, bit18...bit0 data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... address bit23, bit21, bit19...bit1 21 22 23 24 25 26 27 8 bit instruction 12 bit address 4 dummy cycle data output 37 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 19. dual read mode sequence (command 3b) high impedance 2 1 345678 0 sclk si/sio0 so/sio1 cs# 9 10 11 30 31 32 3b(hex) dummy address bit23, bit22, ...bit0 data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... 39 40 41 42 43 8 bit instruction 24 bit address 8 dummy cycle data output figure 20. 4 x i/o read mode sequence (command eb) high impedance 2 1 345678 0 sclk si/sio0 so/sio1 cs# 9 12 10 11 13 14 eb(hex) address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 17 18 19 20 21 22 23 n high impedance wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles 4 dummy cycles performance enhance indicator (note) data output note: 1. hi-impedance is inhibited for the two clock cycles. 2. p7p3, p6p2, p5p1 & p4p0 (toggling) is inhibited. 38 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 21. 4 x i/o read enhance performance mode sequence (command eb) high impedance 2 1 345678 0 sclk si/sio0 so/sio1 cs# 9 12 10 11 13 14 eb(hex) address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 n+1 ........... ...... ........... ........... n+7 n+9 n+13 17 18 19 20 21 22 23 n high impedance wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles 4 dummy cycles performance enhance indicator (note) data output sclk si/sio0 so/sio1 cs# address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 6 address cycles 4 dummy cycles performance enhance indicator (note) data output note: performance enhance mode, if p7=p3 & p6=p2 & p5=p1 & p4=p0 (toggling), ex: a5, 5a, 0f reset the performance enhance mode, if p7=p3 or p6=p2 or p5=p1 or p4=p0, ex: aa, 00, ff 39 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 22. quad read mode sequence (command 6b) high impedance 2 1 345678 0 sclk si/sio0 so/sio1 cs# 9 32 30 31 6b(hex) dummy address bit23, bit22..bit0 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 33 38 39 40 41 42 43 high impedance wp#/sio2 data bit6 bit2, bit6.... high impedance nc/sio3 data bit7 bit3, bit7.... 8 bit instruction 24 bit address 8 dummy cycle data output 40 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 23. page program (pp) sequence (command 02) figure 24. 4 x i/o page program (4pp) sequence (command 38) 42 41 43 44 45 46 47 48 49 50 52 53 54 55 40 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 24-bit address 0 765432 0 1 data byte 1 39 51 765432 0 1 data byte 2 765432 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 765432 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02 command 20 21 17 16 12 8 4 0 13 9 5 1 4 4 4 4 0 0 0 0 5 5 5 5 1 1 1 1 2 1 3456789 6 address cycle data byte 1 data byte 2 data byte 3 data byte 4 0 22 18 14 10 6 2 23 19 15 11 7 3 6 6 6 6 2 2 2 2 7 7 7 7 3 3 3 3 sclk cs# si/sio0 so/sio1 nc/sio3 wp#/sio2 38 command 10 11 12 13 14 15 16 17 18 19 20 21 41 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 26. sector erase (se) sequence (command 20) figure 27. block erase (be) sequence (command d8) figure 25. continously program (cp) mode sequence with hardware detection (command ad) note: (1) during cp mode, the valid commands are cp command (ad hex), wrdi command (04 hex), rdsr com - mand (05 hex), and rdscur command (2b hex). (2) once an internal programming operation begins, cs# goes low will drive the status on the so pin and cs# goes high will return the so pin to tri-state. (3) to end the cp mode, either reaching the highest unprotected address or sending write disable (wrdi) command (04 hex) may achieve it and then it is recommended to send rdsr command (05 hex) to verify if cp mode is ended. note: se command is 20(hex). note: be command is d8(hex). cs# sclk 0 1 6 7 8 9 si command ad (hex) 30 31 31 s0 high impedance 32 47 48 status (2) data in 24-bit address byte 0, byte1 0 1 valid command (1) data in byte n-1, byte n 6 7 8 20 21 22 23 0 04 (hex) 24 7 0 7 05 (hex) 8 24 bit address 2 1 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20 command 24 bit address 2 1 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si d8 command 42 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 28. chip erase (ce) sequence (command 60 or c7) figure 29. deep power-down (dp) sequence (command b9) figure 30. release from deep power-down and read electronic signature (res) sequence (command ab) note: ce command is 60(hex) or c7(hex). 2 1 34567 0 60 or c7 sclk si cs# command 2 1 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9 command 23 2 1 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 765432 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so ab command 43 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 notes: (1) add=00h will output the manufacturer's id frst and add=01h will output device id frst (2) instruction is either 90(hex) or ef(hex) or df(hex). figure 31. release from deep power-down (rdp) sequence (command ab) figure 32. read electronic manufacturer & device id (rems) sequence (command 90 or ef or df) 2 1 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so ab command 15 14 13 3 2 1 0 2 1 3456789 10 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 765432 0 1 35 31 30 29 28 sclk si cs# so sclk si cs# so x 90 high-z command 44 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 33. power-up timing note: vcc (max.) is 3.6v and vcc (min.) is 2.7v. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). note: 1. the parameter is characterized only. table 9. power-up timing v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low 200 us 45 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 notes : 1. sampled, not 100% tested. 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "ac characteristics" table. symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v operating conditions at device power-up and power-down ac timing illustrated in figure 34 and figure 35 are for the supply voltages and the control signals at device power- up and power-down. if the timing in the fgures is ignored, the device will not operate correctly . during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 34. ac timing at device power-up sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd 46 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 figure 35. power-down sequence c s # sclk v c c during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. 47 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 erase and programming performance latch-up characteristics min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. parameter min. typ. (1) max. (2) unit chip unprotect 40 100 ms sector erase cycle time 60 300 ms block erase cycle time 0.7 2 s chip erase cycle time 25 50 s byte program time (via page program command) 9 300 us page program cycle time 1.4 5 ms erase/program cycle 100,000 cycles block write lock protection 9 300 us note: 1. typical program and erase time assumes the following conditions: 25 c, 3.3v, and checker board pattern. 2. under worst conditions of 85 c and 2.7v. 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming com - mand. 4. erase/program cycles comply with jedec: jesd-47 & jesd22-a117 standard. data retention parameter condition min. max. unit data retention 55?c 20 years 48 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 ordering information part no. clock (mhz) operating current max. (ma) standby current max. (ua) temperature package remark MX25L3255DM2I-10G 104 25 20 -40c~85c 8-sop (200mil) pb-free mx25l3255dxci-10g 104 25 20 -40c~85c 24-bga (6mmx8mm) pb-free 49 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 part name description mx 25 l 10 m2 i g option: g: pb-free speed: 10: 104mhz temperature range: i: industrial (-40?c to 85?c) package: m2: 200mil 8-sop xc: 24-bga (6mmx8mm) density & mode: 3255d: 32mb secure flash type: l: 3v device: 25: serial flash 3255d 50 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 package information 51 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 52 mx25l3255d p/n: pm1431 rev. 1.1, sep. 09, 2010 revision history revision no. description page date 0.01 1. added 24-ball bga package p6,8,45,46 dec/10/2008 p48 2. added read block write lock status (rdblock) p16,18,34 3. modifed figure 19. 4 x i/o read mode sequence (command eb) p36 0.02 1. removed "low vcc write inhibit" function p5,10,26, mar/11/2009 47,51 2. changed "advanced information" into "preliminary" p5 3. revised read status register and added qe/srwd bit p18 4. revised ac charateristics: tch (1) and tcl (1) 5/5 to 4.5/4.5 p30 5. removed "advanced information" p45-46 6. removed qe bit/srwd bit status register information p18,22 7. removed icc3 p29 8. modifed tch/tcl from 4.5/4.5ns to 4.7/4.7ns p30 9. modifed data retention from 10 years to 20 years p5 0.03 1. aligned to complete version mar/13/2009 1.0 1. removed "preliminary" p5 mar/18/2010 2. corrected wrong memory type id data p17 3. removed loading from clock rate p5,28,30 4. removed undefned spec: tqlqh and tqhql p31 5. modifed figure 32. ac timing at device power-up p43 6. added figure 33. power-down sequence p44 1.1 1. added dread mode/qread mode p5,14,15,20 sep/09/2010 p21,37,39 2. modifed storage temperature from -55c to 125c to p28 -65c to 150c 3. modifed figure 26 p41 4. added table for data retention p47 mx25l3255d 53 macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substan - tial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications. copyright? macronix international co., ltd. 2008~2010. all rights reserved. macronix, mxic, mxic logo, mx logo, mxsmio , are trademarks or registered trademarks of macronix international co., ltd.. the names and brands of other companies are for identifcation purposes only and may be claimed as the property of the respective companies. for the contact and order information, please visit macronixs web site at: http://www.macronix.com macronix international co., ltd. reserves the right to change product and specifcations without notice. |
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